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2 edition of 8-bit, 1-Gsample/s folding-interpolating analog-to-digital converter. found in the catalog.

8-bit, 1-Gsample/s folding-interpolating analog-to-digital converter.

Wei An

8-bit, 1-Gsample/s folding-interpolating analog-to-digital converter.

by Wei An

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  • 24 Currently reading

Published by National Library of Canada in Ottawa .
Written in English


Edition Notes

Thesis (M.A.Sc.) -- University of Toronto, 2000.

SeriesCanadian theses = -- Thèses canadiennes
The Physical Object
Pagination1 microfiche : negative. --
ID Numbers
Open LibraryOL19563516M
ISBN 100612503828

A 5 GS/s 8-bit analog-to-digital converter (ADC) implemented in μm SiGe BiCMOS technology has been demonstrated. The proposed ADC is based on two-channel time-interleaved architecture, and each sub-ADC employs a two-stage cascaded folding and interpolating topology of radix An open loop track-and-hold amplifier with enhanced linearity is designed to meet the dynamic performance Author: Dong Wang, Jian Luan, Xuan Guo, Lei Zhou, Danyu Wu, Huasen Liu, Hao Ding, Jin Wu, Xinyu Liu. bit Msamples/sec digital-to-analog converter. Measurement results of Msamples/s bit converter A bit 1-Gsample/s Nyquist digital-to-analog con­ verter Current matrix floor plan Switch and latch circuit Measurement results of 1-Gsample/s bit converter.

In this paper, a CMOS analog-to-digital converter (ADC) with an 8-bit MSPS at V is designed. The architecture of the proposed ADC is based on a Folding ADC with a cascaded-folding and a cascaded-interpolation structure. A self-linearized pre-amplifier with source degeneration technique and a. Y. Li, “Design of high speed folding and interpolating analog-to-digital converter,” Ph.D. Diss., Texas A&M Univ., May Google Scholar A. G. W. Venes and R. J. van de Plassche, “An MHz, 8-b CMOS folding A/D converter with distributed track-and-hold preprocessing,” IEEE J. Solid-State Circuits, vol. 31, pp. –, Dec Author: Armin Tajalli, Yusuf Leblebici.

×Close. The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. A 6 b GSample/s CMOS A/D converter, IEEE International Solid-State Circuits Conference, pp. –, , Digest of Technical Papers. ISSCC. ISSCC. Google Scholar.


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8-bit, 1-Gsample/s folding-interpolating analog-to-digital converter by Wei An Download PDF EPUB FB2

This paper deals with the design and implementation of an 8-bit, 1-Gsample/s folding-interpolating analog-to-digital converter using a conventional µm self-aligned, double polysilicon bipolar. This paper deals with the design and implementation of an 8-bit, 1-Gsample/s 8-bit analog-to-digital converter using a conventional µm self-aligned, double polysilicon bipolar process with maximum unity gain cutoff frequency fTof 25GHz.

An 8-bit 2-Gsamples/s folding-interpolating analog-to-digital converter in SiGe technology. IEEE Journal of Solid-State Circuits, 39 (1), Google Scholar Cross Ref. An 8-bit, GS/s Folding-Interpolating Analog-to-Digital Converter Master of Applied Science, Shohreh Ghetmiri Department of Electrical and Computer Engineering University of Toronto Abstract The motivation behind this work is to target the demand for high-speed medium-resolution ADCs for satellite communication by: An 8=Bit, l&le/s Folding-Interpolating Analog-to- Digitai Converter Master of Applied Science, 2ûûû Wei An Department of Electricai and Cornputer Engineering University of Toronto This thesis deals with the design and implementation of an 8-bit, 1-Gsampleh folding- interpolating analog-to-digital converter using a conventional pn self-aligned, doubleCited by:   Abstract: This paper presents an 8-bit low power cascaded folding and interpolating analog-to-digital converter (ADC) with Current Mode Logic (CML).

A 8-bit in the number of comparators, equal to the number of times the signal is folded, is obtained. To ensure high speed and low noise, the CML is used. Abstract: This paper deals with the design and implementation of an 8-bit 2-Gsample/s folding-interpolating analog-to-digital converter (ADC) using a SiGe technology with a unity gain cutoff frequency f/sub T/ of 47 GHz.

The high-speed high-resolution ADC has applications in direct IF sampling receivers for wideband communication systems. The converter occupies an area of mm/spl Cited by:   Abstract: This paper describes the design of a 8-bit CMOS folding and interpolating Analog to Digital Converter (ADC) with high speed comparator.

The objective of this paper is to design and identify the performance of the ADC with two types of by: 3. Analog to Digital Converters - ADC High Spd Lo Pwr 4-CH Simult Sampling 12B Analog to Digital Converter Product details. Item Weight: ounces Shipping Weight: ounces (View shipping rates and policies) ASIN: B00AZVLBNY; Item model number: ADASZ An analog to digital converter is a mixed signal device which converts an analog electrical signal into digital data.

Thus they form the front end of any d Implementation of 8-bit folding and interpolating analog to digital converter in 90nm technology - IEEE Conference PublicationAuthor: Amol Phad, Vaibhav Ingale, Rashmi Vaidya, Pratibha Shingare.

8-bit ADC. Cascaded folding scheme is applied to an 8-bit ADC. The following two tables summarize the design constraints and performance of an 8-bit ADC for various circuit parameters according to SIMULINK simulation.

The performance is obtained under the typical parameter values specified in Table 2. Fig. illustrate performance of File Size: 1MB.

Abstract: Some non-ideal factors during circuit design of folding and interpolating analog to digital converter (FIADC) are analyzed and summarized in this paper. Based on Matlab software, a 8 bit classic FIADC has been modeled and effects of these non-ideal factors has been validated such as reference voltage varies which caused by the resistance errors, output voltage offset of the track Author: Ruoyuan Qu, Zhuohong Du, Ming Zhu, Nan Li, Hengjing Zhu.

This paper presents an 8-bit low power cascaded folding and interpolating analog-to-digital converter (ADC) with Current Mode Logic (CML). A reduction in the number of comparators, equal to the number of times the signal is folded, is obtained. To ensure high speed and low noise, the CML is used.

The circuit is implemented in a ??m CMOS technology, and measures mm?. mm (including. A single-channel 2 GS/s 8-bit analog-to-digital converter in 90 nm CMOS process technology is presented.

It utilizes cascade folding architecture, which incorporates an additional inter-stage. This paper presents an 8-bit low power cascaded folding and interpolating analog-to-digital converter (ADC).

A reduction in the number of comparators, equal to the number of times the signal is folded, is obtained. The interleaved architecture is used to improve the sampling rate of the ADC.

The circuit including a bandgap is implemented in a ??m CMOS technology, and measures mm?. An 8-bit MHz full-Nyquist analog-to-digital (A/D) converter using a folding and interpolation architecture is presented.

In a folding system a multiple use of comparator stages is implemented. Folding and Interpolating ADCs have been shown to be an effective means of digitization of high bandwidth signals at intermediate resolution.

The book focuses on design of low power Folding and Interpolating ADC using novel cascaded folding amplifier. The architecture improvements and optimization of various sub blocks are discussed in the : Shruti Oza, Niranjan Devashrayee.

Ultra high speed and moderate resolution ADCs with low latency are demanded in many applications. A 4-GS/s 8-bit ADC is implemented in the μm SiGe BiCMOS technology.

It is based on the two-channel time-interleaved architecture and each sub-ADC employs the two-stage cascaded folding and interpolating topology which guarantees the low-latency by: 1. This paper presents the analysis, design and experimental results of a 12 bits, 50 MSample/s Analog-to-Digital Converter, based on a Cascaded Folding and Interpolating architecture.

The ADC is optimized for digital telecommunication by: 1. An 8-bit, MSPS folding and interpolating analog-to-digitalconverter, ADC, has been implemented in a µmBiCMOS-process. It achieves effective bits with a power dissipationof mW. The active area is 4mm 2. The implementationand measured results are by: 3.

An 8-bit MS/s folding and interpolating analog-to-digital converter (ADC) using the continuous-time auto-zero technique is presented.

Compared with the conventional architecture, it can improve. A 1-GS/s 6-bit two-channel time-interleaved folding and interpolating analog-to-digital converter (ADC) is presented in this article. For low voltage applications, input-connection-improved active interpolating amplifiers and cascaded folding amplifiers have been applied.

A single front-end track-and-hold (T/H) circuit is used to avoid the sampling-time mismatches between the channels.A single-channel GS/s 8-bit Voltage-Buffer-Free Pipelined-Folding-Interpolating analog-to-digital converter (PL-FAI-ADC) is presented.

Grouped T/H blocks are adopted to cancel the voltage buffer between the T/H block and the pre-amplifiers array. A new full-digital T/H switch is proposed to cancel the bootstrapped capacitor, which can save the chip area grandly.